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? motorola, inc., 2003 m68hc11erg/ad rev. 2, 10/2003 m68hc11e series programming reference guide reference guide block diagram pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc4/addr4/data4 pc3/addr3/data3 pc2/addr2/data2 pc1/addr1/data1 pc0/addr0/data0 mode control osc clock logic interrupt logic eeprom (see table) ram (see table) serial peripheral interface spi serial communication interface sci m68hc11 cpu a/d converter control port d port e pe7/an7 txd rxd ss sck mosi miso pd5/ss pd0/rxd stra/as strb/r/w address/data bus expansion address as strobe and handshake parallel i/o strb stra control port c port b pb7/addr15 port a pa7/pai timer system cop pulse accumulator oc2 oc3 oc4 oc5/ic4/oc1 ic1 ic2 ic3 pai periodic interrupt moda/ lir modb/ v stby xtal extal e irq xirq /v ppe* reset pd4/sck pd3/mosi pd2/miso pd1/txd r/w pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 pa2/ic1 pa1/ic2 pa0/ic3 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe6/an6 pe5/an5 pe4/an4 pe3/an3 pe2/an2 pe1/an1 pe0/an0 v dd v ss v rh v rl * v ppe applies only to devices with eprom/otprom. rom or eprom (see table) mc68hc11e0 device 512 512 512 512 768 768 ram ? ? 12 k ? 20 k ? rom ? ? ? 12 k ? 20 k eprom ? 512 512 512 512 512 eeprom mc68hc11e1 mc68hc11e9 mc68hc711e9 MC68HC11E20 mc68hc711e20 256 ? ? 2048 mc68hc811e2
m68hc11erg/ad 2 m68hc11e series programming reference guide motorola devices covered in thi s reference guide m68hc11e series programming model device ram rom eprom eeprom mc68hc11e0 512 ? ? ? mc68hc11e1 512 ? ? 512 mc68hc11e9 512 12k ? 512 mc68hc711e9 512 ? 12k 512 MC68HC11E20 768 20k ? 512 mc68hc711e20 768 ? 10k 512 mc68hc811e2 256 ? ? 2048 8-bit accumulators a & b 70 70 15 0 ab d ix iy sp pc 70 c v z n i h x s or 16-bit double accumulator d index register x index register y stack pointer program counter carry/borrow from msb overflow zero negative i-interrupt mask half carry (from bit 3) x-interrupt mask stop disable condition codes
m68hc11erg/ad crystal dependent timer summary motorola m68hc11e series programming reference guide 3 crystal dependent timer summary selected crystal common xtal frequencies 4.0 mhz 8.0 mhz 12.0 mhz cpu clock (e) 1.0 mhz 2.0 mhz 3.0 mhz cycle time (1/e) 1000 ns 500 ns 333 ns pulse accumulator (in gated mode) (e/2 6 ) (e/2 14 ) 1 count ? overflow ? 64.0 s 16.384 ms 32.0 s 8.192 ms 21.330 s 5.491 ms pr[1:0] main timer count rates (e/1) (e/2 16 ) 0 0 1 count? overflow ? 1.0 s 65.536 ms 500 ns 32.768 ms 333 ns 21.845 ms (e/4) (e/2 18 ) 0 1 1 count? overflow ? 4.0 s 262.14 ms 2.0 s 131.07 ms 1.333 s 87.381 ms (e/8) (e/2 19 ) 1 0 1 count? overflow ? 8.0 s 524.29 ms 4.0 s 262.14 ms 2.667 s 174.76 ms (e/16) (e/2 20 ) 1 1 1 count? overflow ? 16.0 s 1.049 s 8.0 s 524.29 ms 5.333 s 349.52 ms rtr[1:0] periodic (rti) interrupt rates (e/2 13 ) (e/2 14 ) (e/2 15 ) (e/2 16 ) 0 0 0 1 1 0 1 1 8.192 ms 16.384 ms 32.768 ms 65.536 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 2.731 ms 5.461 ms 10.923 ms 21.845 ms cr[1:0] cop watchdog timeout rates (e/2 15 ) (e/2 17 ) (e/2 19 ) (e/2 21 ) 0 0 0 1 1 0 1 1 32.768 ms 131.072 ms 524.288 ms 2.097 s 16.384 ms 65.536 ms 262.14 ms 1.049 s 10.923 ms 43.691 ms 174.76 ms 699.05 ms (e/2 15 ) timeout tolerance (?0 ms/+...) 32.8 ms 16.4 ms 10.9 ms
m68hc11erg/ad 4 m68hc11e series programming reference guide motorola interrupt vector assignments vector address interrupt source ccr mask bit local mask ffc0, c1 ? ffd4, d5 reserved ? ? ffd6, d7 sci serial system (1) sci receive data register full sci receiver overrun sci transmit data register empty sci transmit complete sci idle line detect 1. interrupts generated by sci; read scsr to determine source. refer to hprio register to determine priority of interrupt. i rie rie tie tcie ilie ffd8, d9 spi serial transfer complete i spie ffda, db pulse accumulator input edge i paii ffdc, dd pulse accumulator overflow i paovi ffde, df timer overflow i toi ffe0, e1 timer input capture 4/output compare 5 i i4/o5i ffe2, e3 timer output compare 4 i oc4i ffe4, e5 timer output compare 3 i oc3i ffe6, e7 timer output compare 2 i oc2i ffe8, e9 timer output compare 1 i oc1i ffea, eb timer input capture 3 i ic3i ffec, ed timer input capture 2 i ic2i ffee, ef timer input capture 1 i ic1i fff0, f1 real-time interrupt i rtii fff2, f3 irq (external pin) i none fff4, f5 xirq pin x none fff6, f7 software interrupt none none fff8, f9 illegal opcode trap none none fffa, fb cop failure none nocop fffc, fd clock monitor fail none cme fffe, ff reset none none
m68hc11erg/ad m68hc11e series memory maps motorola m68hc11e series programming reference guide 5 m68hc11e series memory maps figure 1. memory map for mc68hc11e0 figure 2. memory map for mc68hc11e1 ffc0 ffff normal modes interrupt vectors 64-byte register block 512 bytes ram bootstrap special test ext 0000 1000 103f bf00 expanded bfff bfc0 bfff special modes interrupt vectors boot rom ext ext 01ff ext $0000 $1000 $b600 $d000 $ffff ffc0 ffff normal modes interrupt vectors 64-byte register block 512 bytes ram bootstrap special test ext $0000 $1000 $b600 $d000 $ffff 0000 1000 103f bf00 expanded bfff bfc0 bfff special modes interrupt vectors b600 b7ff 512 bytes eeprom boot rom ext ext ext 01ff ext ext
m68hc11erg/ad 6 m68hc11e series programming reference guide motorola figure 3. memory m ap for mc68hc(7)11e9 figure 4. memory map for mc68hc(7)11e20 ffc0 ffff normal modes interrupt vectors 64-byte register block 512 bytes ram single chip bootstrap special test ext $0000 $1000 $b600 $d000 $ffff 0000 1000 103f bf00 expanded d000 ffff bfff bfc0 bfff special modes interrupt vectors b600 b7ff 512 bytes eeprom 12 kbytes rom/eprom boot rom ext ext ext 01ff ext ext 9000 afff 8 kbytes rom/eprom * * 20 kbytes rom/eprom are contained in two segments of 8 kbytes and 12 kbytes each. ffc0 ffff normal modes interrupt vectors 64-byte register block 768 bytes ram single chip bootstrap special test ext $0000 $1000 $b600 $d000 $ffff 0000 1000 103f bf00 expanded d000 ffff bfff bfc0 bfff special modes interrupt vectors b600 b7ff 512 bytes eeprom 12 kbytes rom/eprom * boot rom ext ext 02ff ext ext $9000 ext ext ext
m68hc11erg/ad m68hc11e series memory maps motorola m68hc11e series programming reference guide 7 figure 5. memory map for mc68hc811e2 ffc0 ffff normal modes interrupt vectors 64-byte register block 256 bytes ram single chip bootstrap special test ext $0000 $1000 $f800 $ffff 0000 1000 103f bf00 expanded f800 ffff bfff bfc0 bfff special modes interrupt vectors 2048 bytes eeprom boot rom ext ext 00ff ext
m68hc11erg/ad 8 m68hc11e series programming reference guide motorola opcode maps page 1 acca accb inh inh rel inh acca accb ind,x ext imm dir ind,x ext imm dir ind,x ext 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3456789abcdef 0000 0 test sba bra tsx neg sub 0 0001 1 nop cba brn ins cmp 1 0010 2 idiv brset bhi pula sbc 2 0011 3 ediv brclr bls pulb com subd addd 3 0100 4 lsrd bset bcc des lsr and 4 0101 5 asld bclr bcs txs bit 5 0110 6 tap tab bne psha ror lda 6 0111 7 tpa tba beq pshb asr sta sta 7 1000 8 inx page 2 bvc pulx asl eor 8 1001 9 dex daa bvs rts rol adc 9 1010 a clv page 3 bpl abx dec ora a 1011 b sev aba bmi rti add b 1100 c clc bset bge pshx inc cpx ldd c 1101 d sec bclr blt mul tst bsr jsr page 4 std d 1110 e cli brset bgt wai jmp lds ldx e 1111 f sei brclr ble swi clr xgdx sts stop stx f 0 1 2 3456789abcdef msb lsb dir ind,x
motorola m68hc11e series programming reference guide 9 m68hc11erg/ad opcode maps page 2 (18xx) acca accb inh inh ind,y imm dir ind,x ext imm dir ind,x ext 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3456789abcdef 0000 0 tsy neg sub sub 0 0001 1 cmp cmp 1 0010 2 sbc sbc 2 0011 3 com subd addd 3 0100 4 lsr and and 4 0101 5 tys bit bit 5 0110 6 ror lda lda 6 0111 7 asr sta sta 7 1000 8 iny puly asl eor eor 8 1001 9 dey rdl adc adc 9 1010 a aby dec ora ora a 1011 b add add b 1100 c bset pshy inc cpy ldd c 1101 d bclr tst jsr std d 1110 e brset jmp lds ldy e 1111 f brclr clr xgdy sts sty f 0 1 2 3456789abcdef msb lsb ind,y
m68hc11erg/ad 10 m68hc11e series programming reference guide motorola page 3 (1axx) acca accb imm dir ind,x ext ind,x 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3456789abcdef 0000 0 0 0001 1 1 0010 2 2 0011 3 cpd 3 0100 4 4 0101 5 5 0110 6 6 0111 7 7 1000 8 8 1001 9 9 1010 a a 1011 b b 1100 c cpy c 1101 d d 1110 e ldy e 1111 f sty f 0 1 2 3456789abcdef msb lsb
motorola m68hc11e series programming reference guide 11 m68hc11erg/ad opcode maps page 4 (cdxx) acca accb ind,y ind,y 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3456789abcdef 0000 0 0 0001 1 1 0010 2 2 0011 3 cpd 3 0100 4 4 0101 5 5 0110 6 6 0111 7 7 1000 8 8 1001 9 9 1010 a a 1011 b b 1100 c cpx c 1101 d d 1110 e ldx e 1111 f stx f 0 1 2 3456789abcdef msb lsb
m68hc11erg/ad 12 m68hc11e series programming reference guide motorola simple branches simple conditional branches signed conditional branches unsigned condi tional branches bit manipulation branches brclr branch if all selected bits are clear (opcode) (operand addr) (mask) (rel offset) m mm = 0? m = operand in memory; mm = mask brset branch if all selected bits are set (opcode) (operand addr) (rel offset) (m ) mm = 0? m = operand in memory; mm = mask mnemonic opcode cycles bra 20 3 brn 21 3 bsr 8d 7 test true false instruction opcode instruction opcode n = 1 bmi 2b bpl 2a z = 1 beq 27 bne 26 v = 1 bvs 29 bvc 28 c = 1 bcs 25 bcc 24 test true false instruction opcode instruction opcode r > m bgt 2e ble 2f r m bge 2c blt 2d r = m beq 27 bne 26 r mble 2f bgt 2e r < m blt 2d bge 2c test true false instruction opcode instruction opcode r > m bhi 22 bls 23 r m bhs/bcc 24 bl0/bcs 25 r = m beq 27 bne 26 r mbls 23 bhi 22 r < m blo/bcs 25 bhs/bcc 24
m68hc11erg/ad instruction set motorola m68hc11e series programming reference guide 13 instruction set refer to table 1 , which shows all the m68hc11 instructions in all possible addressing modes. for each instruction, the table shows the operand construction, the number of machine c ode bytes, and execution time in cpu e-clock cycles. table 1. instruction set (sheet 1 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c aba add accumulators a + b ? ainh1b?2?? ? ? ???? abx add b to x ix + (00 : b) ? ix inh 3a ? 3 ???????? aby add b to y iy + (00 : b) ? iy inh 18 3a ? 4 ???????? adca (opr) add with carry to a a + m + c ? aa imm adir aext aind,x aind,y 89 99 b9 a9 18 a9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adcb (opr) add with carry to b b + m + c ? bb imm bdir bext bind,x bind,y c9 d9 f9 e9 18 e9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adda (opr) add memory to a a + m ? a a imm adir aext aind,x aind,y 8b 9b bb ab 18 ab ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addb (opr) add memory to b b + m ? bbimm bdir bext bind,x bind,y cb db fb eb 18 eb ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addd (opr) add 16-bit to d d + (m : m + 1) ? dimm dir ext ind,x ind,y c3 d3 f3 e3 18 e3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? anda (opr) and a with memory a m ? aa imm a dir a ext aind,x aind,y 84 94 b4 a4 18 a4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? andb (opr) and b with memory b m ? bbimm bdir bext bind,x bind,y c4 d4 f4 e4 18 e4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? asl (opr) arithmetic shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? asla arithmetic shift left a a inh 48 ? 2 ???? ???? aslb arithmetic shift left b b inh 58 ? 2 ???? ???? asld arithmetic shift left d inh 05 ? 3 ? ? ? ? ???? c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0
m68hc11erg/ad 14 m68hc11e series programming reference guide motorola asr arithmetic shift right ext ind,x ind,y 77 67 18 67 hh ll ff ff 6 6 7 ???? ???? asra arithmetic shift right a a inh 47 ? 2 ???? ???? asrb arithmetic shift right b b inh 57 ? 2 ???? ???? bcc (rel) branch if carry clear ? c = 0 rel 24rr 3 ???????? bclr (opr) (msk) clear bit(s) m (mm ) ? m dir ind,x ind,y 15 1d 18 1d dd mm ff mm ff mm 6 7 8 ???? ?? 0? bcs (rel) branch if carry set ? c = 1 rel 25rr 3 ???????? beq (rel) branch if = zero ? z = 1 rel 27 rr 3 ? ? ? ? ? ? ? ? bge (rel) branch if ? zero ? n v = 0 rel 2crr 3 ???????? bgt (rel) branch if > zero ? z + (n v) = 0 rel 2err 3 ???????? bhi (rel) branch if higher ? c + z = 0 rel 22rr 3 ???????? bhs (rel) branch if higher or same ? c = 0 rel 24rr 3 ???????? bita (opr) bit(s) test a with memory a m a imm adir aext aind,x aind,y 85 95 b5 a5 18 a5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? bitb (opr) bit(s) test b with memory b m b imm bdir bext bind,x bind,y c5 d5 f5 e5 18 e5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ble (rel) branch if ? zero ? z + (n v) = 1 rel 2frr 3 ???????? blo (rel) branch if lower ? c = 1 rel 25 rr 3 ? ? ? ? ? ? ? ? bls (rel) branch if lower or same ? c + z = 1 rel 23rr 3 ???????? blt (rel) branch if < zero ? n v = 1 rel 2drr 3 ???????? bmi (rel) branch if minus ? n = 1 rel 2b rr 3 ? ? ? ? ? ? ? ? bne (rel) branch if not = zero ? z = 0 rel 26rr 3 ???????? bpl (rel) branch if plus ? n = 0 rel 2a rr 3 ? ? ? ? ? ? ? ? bra (rel) branch always ? 1 = 1 rel 20 rr 3 ? ? ? ? ? ? ? ? brclr(opr) (msk) (rel) branch if bit(s) clear ? m mm = 0 dir ind,x ind,y 13 1f 18 1f dd mm rr ff mm rr ff mm rr 6 7 8 ???????? brn (rel) branch never ? 1 = 0 rel 21rr 3 ???????? brset(opr) (msk) (rel) branch if bit(s) set ? (m ) mm = 0 dir ind,x ind,y 12 1e 18 1e dd mm rr ff mm rr ff mm rr 6 7 8 ???????? bset (opr) (msk) set bit(s) m + mm ? mdir ind,x ind,y 14 1c 18 1c dd mm ff mm ff mm 6 7 8 ???? ?? 0? bsr (rel) branch to subroutine see figure 3?2 rel 8d rr 6 ? ? ? ? ? ? ? ? bvc (rel) branch if overflow clear ? v = 0 rel 28rr 3 ???????? table 1. instruction set (sheet 2 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c c b7 b0 c b7 b0 c b7 b0
m68hc11erg/ad instruction set motorola m68hc11e series programming reference guide 15 bvs (rel) branch if overflow set ? v = 1 rel 29rr 3 ???????? cba compare a to b a ? b inh 11 ? 2 ? ? ? ? ???? clc clear carry bit 0 ? c inh 0c ? 2 ??????? 0 cli clear interrupt mask 0 ? i inh 0e ? 2 ??? 0 ???? clr (opr) clear memory byte 0 ? mext ind,x ind,y 7f 6f 18 6f hh ll ff ff 6 6 7 ???? 0 1 0 0 clra clear accumulator a 0 ? a a inh 4f ? 2 ? ? ? ? 0 1 0 0 clrb clear accumulator b 0 ? b b inh 5f ? 2 ? ? ? ? 0 1 0 0 clv clear overflow flag 0 ? v inh 0a ? 2 ?????? 0 ? cmpa (opr) compare a to memory a ? m a imm adir aext aind,x aind,y 81 91 b1 a1 18 a1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? cmpb (opr) compare b to memory b ? m b imm bdir bext bind,x bind,y c1 d1 f1 e1 18 e1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? com (opr) ones complement memory byte $ff ? m ? mext ind,x ind,y 73 63 18 63 hh ll ff ff 6 6 7 ???? ?? 01 coma ones complement a $ff ? a ? aa inh 43 ? 2 ???? ?? 01 comb ones complement b $ff ? b ? bb inh 53 ? 2 ???? ?? 01 cpd (opr) compare d to memory 16-bit d ? m : m + 1 imm dir ext ind,x ind,y 1a 83 1a 93 1a b3 1a a3 cd a3 jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? cpx (opr) compare x to memory 16-bit ix ? m : m + 1 imm dir ext ind,x ind,y 8c 9c bc ac cd ac jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? cpy (opr) compare y to memory 16-bit iy ? m : m + 1 imm dir ext ind,x ind,y 18 8c 18 9c 18 bc 1a ac 18 ac jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? daa decimal adjust a adjust sum to bcd inh 19 ? 2 ? ? ? ? ???? dec (opr) decrement memory byte m ? 1 ? mext ind,x ind,y 7a 6a 18 6a hh ll ff ff 6 6 7 ???? ??? ? deca decrement accumulator a a ? 1 ? aainh 4a ? 2???? ??? ? decb decrement accumulator b b ? 1 ? bbinh 5a ? 2???? ??? ? table 1. instruction set (sheet 3 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c
m68hc11erg/ad 16 m68hc11e series programming reference guide motorola des decrement stack pointer sp ? 1 ? sp inh 34 ? 3 ???????? dex decrement index register x ix ? 1 ? ix inh 09 ? 3 ? ? ? ? ? ? ?? dey decrement index register y iy ? 1 ? iy inh 18 09 ? 4 ? ? ? ? ? ? ?? eora (opr) exclusive or a with memory a m ? a a imm adir aext aind,x aind,y 88 98 b8 a8 18 a8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? eorb (opr) exclusive or b with memory b m ? b b imm bdir bext bind,x bind,y c8 d8 f8 e8 18 e8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? fdiv fractional divide 16 by 16 d / ix ? ix; r ? d inh 03 ? 41 ????? ??? idiv integer divide 16 by 16 d / ix ? ix; r ? d inh 02 ? 41 ????? ? 0 ? inc (opr) increment memory byte m + 1 ? mext ind,x ind,y 7c 6c 18 6c hh ll ff ff 6 6 7 ???? ??? ? inca increment accumulator a a + 1 ? a a inh 4c ? 2 ? ? ? ? ??? ? incb increment accumulator b b + 1 ? b b inh 5c ? 2 ? ? ? ? ??? ? ins increment stack pointer sp + 1 ? sp inh 31 ? 3 ???????? inx increment index register x ix + 1 ? ix inh 08 ? 3 ????? ? ?? iny increment index register y iy + 1 ? iy inh 18 08 ? 4 ????? ? ?? jmp (opr) jump see figure 3?2 ext ind,x ind,y 7e 6e 18 6e hh ll ff ff 3 3 4 ???????? jsr (opr) jump to subroutine see figure 3?2 dir ext ind,x ind,y 9d bd ad 18 ad dd hh ll ff ff 5 6 6 7 ???????? ldaa (opr) load accumulator a m ? a a imm a dir a ext a ind,x a ind,y 86 96 b6 a6 18 a6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ldab (opr) load accumulator b m ? b b imm b dir b ext b ind,x b ind,y c6 d6 f6 e6 18 e6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ldd (opr) load double accumulator d m ? a,m + 1 ? bimm dir ext ind,x ind,y cc dc fc ec 18 ec jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? table 1. instruction set (sheet 4 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c
m68hc11erg/ad instruction set motorola m68hc11e series programming reference guide 17 lds (opr) load stack pointer m : m + 1 ? sp imm dir ext ind,x ind,y 8e 9e be ae 18 ae jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? ldx (opr) load index register x m : m + 1 ? ix imm dir ext ind,x ind,y ce de fe ee cd ee jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? ldy (opr) load index register y m : m + 1 ? iy imm dir ext ind,x ind,y 18 ce 18 de 18 fe 1a ee 18 ee jj kk dd hh ll ff ff 4 5 6 6 6 ???? ?? 0? lsl (opr) logical shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? lsla logical shift left a a inh 48 ? 2 ???? ???? lslb logical shift left b b inh 58 ? 2 ???? ???? lsld logical shift left double inh 05 ? 3 ? ? ? ? ???? lsr (opr) logical shift right ext ind,x ind,y 74 64 18 64 hh ll ff ff 6 6 7 ???? 0 ??? lsra logical shift right a a inh 44 ? 2 ???? 0 ??? lsrb logical shift right b b inh 54 ? 2 ???? 0 ??? lsrd logical shift right double inh 04 ? 3 ? ? ? ? 0 ??? mul multiply 8 by 8 a ? b ? d inh 3d ? 10 ??????? ? neg (opr) two?s complement memory byte 0 ? m ? mext ind,x ind,y 70 60 18 60 hh ll ff ff 6 6 7 ???? ???? nega two?s complement a 0 ? a ? aainh 40 ? 2???? ???? negb two?s complement b 0 ? b ? bbinh 50 ? 2???? ???? nop no operation no operation inh 01 ? 2 ? ? ? ? ? ? ? ? oraa (opr) or accumulator a (inclusive) a + m ? a a imm adir aext aind,x aind,y 8a 9a ba aa 18 aa ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? orab (opr) or accumulator b (inclusive) b + m ? b b imm bdir bext bind,x bind,y ca da fa ea 18 ea ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? table 1. instruction set (sheet 5 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0
m68hc11erg/ad 18 m68hc11e series programming reference guide motorola psha push a onto stack a ? stk,sp = sp ? 1 a inh 36 ? 3 ? ? ? ? ? ? ? ? pshb push b onto stack b ? stk,sp = sp ? 1 b inh 37 ? 3 ? ? ? ? ? ? ? ? pshx push x onto stack (lo first) ix ? stk,sp = sp ? 2 inh 3c ? 4 ???????? pshy push y onto stack (lo first) iy ? stk,sp = sp ? 2 inh 18 3c ? 5 ???????? pula pull a from stack sp = sp + 1, a ? stka inh 32 ? 4 ???????? pulb pull b from stack sp = sp + 1, b ? stkb inh 33 ? 4 ???????? pulx pull x from stack (hi first) sp = sp + 2, ix ? stk inh 38 ? 5 ???????? puly pull y from stack (hi first) sp = sp + 2, iy ? stk inh 18 38 ? 6 ???????? rol (opr) rotate left ext ind,x ind,y 79 69 18 69 hh ll ff ff 6 6 7 ???? ???? rola rotate left a a inh 49 ? 2 ? ? ? ? ???? rolb rotate left b b inh 59 ? 2 ? ? ? ? ???? ror (opr) rotate right ext ind,x ind,y 76 66 18 66 hh ll ff ff 6 6 7 ???? ???? rora rotate right a a inh 46 ? 2 ? ? ? ? ???? rorb rotate right b b inh 56 ? 2 ? ? ? ? ???? rti return from interrupt see figure 3?2 inh 3b ? 12 ??????? rts return from subroutine see figure 3?2 inh 39 ? 5 ? ? ? ? ? ? ? ? sba subtract b from a a ? b ? a inh 10 ? 2 ???? ???? sbca (opr) subtract with carry from a a ? m ? c ? aa imm adir aext aind,x aind,y 82 92 b2 a2 18 a2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? sbcb (opr) subtract with carry from b b ? m ? c ? bb imm bdir bext bind,x bind,y c2 d2 f2 e2 18 e2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? sec set carry 1 ? c inh 0d ? 2 ??????? 1 sei set interrupt mask 1 ? i inh 0f ? 2 ??? 1 ???? sev set overflow flag 1 ? v inh 0b ? 2 ?????? 1 ? table 1. instruction set (sheet 6 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0
m68hc11erg/ad instruction set motorola m68hc11e series programming reference guide 19 staa (opr) store accumulator a a ? madir aext aind,x aind,y 97 b7 a7 18 a7 dd hh ll ff ff 3 4 4 5 ???? ?? 0? stab (opr) store accumulator b b ? mbdir bext bind,x bind,y d7 f7 e7 18 e7 dd hh ll ff ff 3 4 4 5 ???? ?? 0? std (opr) store accumulator d a ? m, b ? m + 1 dir ext ind,x ind,y dd fd ed 18 ed dd hh ll ff ff 4 5 5 6 ???? ?? 0? stop stop internal clocks ? inh cf ? 2 ???????? sts (opr) store stack pointer sp ? m : m + 1 dir ext ind,x ind,y 9f bf af 18 af dd hh ll ff ff 4 5 5 6 ???? ?? 0? stx (opr) store index register x ix ? m : m + 1 dir ext ind,x ind,y df ff ef cd ef dd hh ll ff ff 4 5 5 6 ???? ?? 0? sty (opr) store index register y iy ? m : m + 1 dir ext ind,x ind,y 18 df 18 ff 1a ef 18 ef dd hh ll ff ff 5 6 6 6 ???? ?? 0? suba (opr) subtract memory from a a ? m ? aaimm adir aext aind,x aind,y 80 90 b0 a0 18 a0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subb (opr) subtract memory from b b ? m ? baimm adir aext aind,x aind,y c0 d0 f0 e0 18 e0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subd (opr) subtract memory from d d ? m : m + 1 ? dimm dir ext ind,x ind,y 83 93 b3 a3 18 a3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? swi software interrupt see figure 3?2 inh 3f ? 14 ? ? ? 1 ? ? ? ? tab transfer a to b a ? b inh 16 ? 2 ???? ?? 0? tap transfer a to cc register a ? ccr inh 06 ? 2 ??????? tba transfer b to a b ? a inh 17 ? 2 ???? ?? 0? test test (only in test modes) address bus counts inh 00 ? * ? ? ? ? ? ? ? ? tpa transfer cc register to a ccr ? a inh 07 ? 2 ???????? tst (opr) test for zero or minus m ? 0 ext ind,x ind,y 7d 6d 18 6d hh ll ff ff 6 6 7 ???? ?? 00 tsta test a for zero or minus a ? 0 a inh 4d ? 2 ? ? ? ? ?? 00 tstb test b for zero or minus b ? 0 b inh 5d ? 2 ? ? ? ? ?? 00 tsx transfer stack pointer to x sp + 1 ? ix inh 30 ? 3 ???????? table 1. instruction set (sheet 7 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c
m68hc11erg/ad 20 m68hc11e series programming reference guide motorola tsy transfer stack pointer to y sp + 1 ? iy inh 18 30 ? 4 ???????? txs transfer x to stack pointer ix ? 1 ? sp inh 35 ? 3 ???????? tys transfer y to stack pointer iy ? 1 ? sp inh 18 35 ? 4 ???????? wai wait for interrupt stack regs & wait inh 3e ? ** ? ? ? ? ? ? ? ? xgdx exchange d with x ix ? d, d ? ix inh 8f ? 3 ???????? xgdy exchange d with y iy ? d, d ? iy inh 18 8f ? 4 ???????? table 1. instruction set (sheet 8 of 8) mnemonic operation description addressing mode instruction condition codes opcode operand cycles s x h i n z v c cycle * infinity or until reset occurs ** 12 cycles are used beginning with the opcode fetch. a wait stat e is entered which remains in effect for an integer number of mpu e-clock cycles (n) until an interrupt is recognized. finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total). operands dd = 8-bit direct address ($0000?$00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (255) (is added to index) hh = high-order byte of 16-bit extended address ii = one byte of immediate data jj = high-order byte of 16-bit immediate data kk = low-order byte of 16-bit immediate data ll = low-order byte of 16-bit extended address mm = 8-bit mask (set bits to be affected) rr = signed relative offset $80 (?128) to $7f (+127) (offset relative to address following machine code offset byte)) operators ( ) contents of register shown inside parentheses ? is transferred to ? is pulled from stack ? is pushed onto stack boolean and + arithmetic addition symbol except where used as inclusive-or symbol in boolean formula exclusive-or ? multiply : concatenation ? arithmetic subtraction symbol or negation symbol (two?s complement) condition codes ? bit not changed 0 bit always cleared 1 bit always set ? bit cleared or set, depending on operation bit can be cleared, cannot become set
m68hc11erg/ad special operations motorola m68hc11e series programming reference guide 21 special operations ? sp?2 stack rtn h sp?1 rtn l sp 70 pc main program $9d = jsr jsr, jump to subroutine dd next main instr. rtn direct pc main program $ad = jsr ff next main instr. rtn indexed, x pc main program $18 = pre ff next main instr. rtn indexed, y $ad = jsr pc main program $bd = pre ll next main instr. rtn indexed, y hh sp stack ccr sp+1 accb sp+2 acca sp+3 ix h sp+4 ix l sp+5 iy h sp+6 iy l sp+7 rtn h sp+8 ? sp+9 70 rtn l pc interrupt routine $3b = rti ? sp?9 stack ccr sp?8 accb sp?7 acca sp?6 ix h sp?5 ix l sp?4 iy h sp?3 iy l sp?2 rtn h sp?1 sp 70 rtn l pc main program $3f = swi pc main program $3e = wai swi, software interrupt wai, wait for interrupt rti, return from interrupt ? sp?2 stack rtn h sp?1 rtn l sp 70 pc main program $8d = bsr pc main program $39 = rts bsr, branch to subroutine rts, return from subroutine sp stack rtn h sp+1 rtn l ? sp+2 70 legend: rtn = address of next instruction in main program to be executed upon return from subroutine rtn h = most significant byte of return address rtn l = least significant byte of return address ? = stack pointer position after operation is complete dd = 8-bit direct address ( $0000?$00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (255) is added to index hh = high-order byte of 16-bit extended address ll = low-order byte of 16-bit extended address rr = signed relative offset $80 (?128) to $7f (+127) (offset relative to the address following the machine code offset byte)
m68hc11erg/ad 22 m68hc11e series programming reference guide motorola m68hc11e series registers figure 6 provides a summary of the m68hc11e registers. note that the 128-byte register block can be remapped to any 4k boundary. addr. register name bit 7 6 5 4 3 2 1 bit 0 $1000 port a data register (porta) read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: i 0 0 0 i i i i $1001 reserved r r r r r r r r $1002 parallel i/o control register (pioc) read: staf stai cwom hnds oin pls ega invb write: reset: 0 0 0 0 0 u 1 1 $1003 port c data register (portc) read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: indeterminate after reset $1004 port b data register (portb) read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: 0 0 0 0 0 0 0 0 $1005 port c latched register (portcl) read: pcl7 pcl6 pcl5 pcl4 pcl3 pcl2 pcl1 pcl0 write: reset: indeterminate after reset $1006 reserved r r r r r r r r $1007 port c data direction register (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $1008 port d data register (portd) read: 0 0 pd5 pd4 pd3 pd2 pd1 pd0 write: reset: u u i i i i i i $1009 port d data direction register (ddrd) read: ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 0 0 0 0 0 0 0 0 $100a port e data register (porte) read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset: indeterminate after reset = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 6. register a nd control bit assignments (sheet 1 of 6)
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 23 $100b timer compare force register (cforc) read: foc1 foc2 foc3 foc4 foc5 write: reset: 0 0 0 0 0 0 0 0 $100c output compare 1 mask register (oc1m) read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 write: reset: 0 0 0 0 0 0 0 0 $100d output compare 1 data register (oc1d) read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 write: reset: 0 0 0 0 0 0 0 0 $100e timer counter register high (tcnth) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $100f timer counter register low (tcntl) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $1010 timer input capture 1 register high (tic1h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $1011 timer input capture 1 register low (tic1l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1012 timer input capture 2 register high (tic2h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $1013 timer input capture 2 register low (tic2l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1014 timer input capture 3 register high (tic3h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $1015 timer input capture 3 register low (tic3l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1016 timer output compare 1 register high (toc1h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 6. register a nd control bit assignments (sheet 2 of 6)
m68hc11erg/ad 24 m68hc11e series programming reference guide motorola $1017 timer output compare 1 register low (toc1l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $1018 timer output compare 2 register high (toc2h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $1019 timer output compare 2 register low (toc2l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $101a timer output compare 3 register high (toc3h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $101b timer output compare 3 register low (toc3l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $101c timer output compare 4 register high (toc4h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $101d timer output compare 4 register low (toc4l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $101e timer input capture 4/output compare 5 register high (ti4/o5) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $101f timer input capture 4/output compare 5 register low (ti4/o5) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $1020 timer control register 1 (tctl1) read: om2 ol2 om3 ol3 om4 ol4 om5 ol5 write: reset: 0 0 0 0 0 0 0 0 $1021 timer control register 2 (tctl2) read: edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a write: reset: 0 0 0 0 0 0 0 0 $1022 timer interrupt mask 1 register (tmsk1) read: oc1i oc2i oc3i oc4i i4 /o5i ic1i ic2i ic3i write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 6. register a nd control bit assignments (sheet 3 of 6)
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 25 $1023 timer interrupt flag 1 (tflg1) read: oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f write: reset: 0 0 0 0 0 0 0 0 $1024 timer interrupt mask 2 register (tmsk2) read: toi rtii paovi paii pr1 pr0 write: reset: 0 0 0 0 0 0 0 0 $1025 timer interrupt flag 2 (tflg2) read: tof rtif paovf paif write: reset: 0 0 0 0 0 0 0 0 $1026 pulse accumulator control register (pactl) read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset: 0 0 0 0 0 0 0 0 $1027 pulse accumulator count register (pacnt) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1028 serial peripheral control register (spcr) read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset: 0 0 0 0 0 1 u u $1029 serial peripheral status register (spsr) read: spif wcol modf write: reset: 0 0 0 0 0 0 0 0 $102a serial peripheral data i/o register (spdr) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $102b baud rate register (baud) read: tclr scp2 (1) scp1 scp0 rckb scr2 scr1 scr0 write: reset: 0 0 0 0 0 u u u $102c serial communications control register 1 (sccr1) read: r8 t8 m wake write: reset: i i 0 0 0 0 0 0 $102d serial communications control register 2 (sccr2) read: tie tcie rie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $102e serial communications status register (scsr) read: tdre tc rdrf idle or nf fe write: reset: 1 1 0 0 0 0 0 0 1. scp2 adds 39 to sci prescaler and is present only in mc68hc(7)11e20. addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 6. register a nd control bit assignments (sheet 4 of 6)
m68hc11erg/ad 26 m68hc11e series programming reference guide motorola $102f serial communications data register (scdr) read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset: indeterminate after reset $1030 analog-to-digital control status register (adctl) read: ccf scan mult cd cc cb ca write: reset: 0 0 indeterminate after reset $1031 analog-to-digital results register 1 (adr1) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1032 analog-to-digital results register 2 (adr2) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1033 analog-to-digital results register 3 (adr3) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1034 analog-to-digital results register 4 (adr4) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $1035 block protect register (bprot) read: ptcon bprt3 bprt2 bprt1 bprt0 write: reset: 0 0 0 1 1 1 1 1 $1036 eprom programming control register (eprog) (1 ) read: mbe elat excol exrow t1 t0 pgm write: reset: 0 0 0 0 0 0 0 0 1. mc68hc711e20 only $1037 reserved r r r r r r r r $1038 reserved r r r r r r r r $1039 system configuration options register (option) read: adpu csel irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset: 0 0 0 1 0 0 0 0 $103a arm/reset cop timer circuitry register (coprst) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $103b eprom and eeprom programming control register (pprog) read: odd even elat (2) byte row erase eelat epgm write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 6. register a nd control bit assignments (sheet 5 of 6)
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 27 a/d control/status register (adctl) ccf ? conversion complete flag this bit is set after an a/d conversion cycle and cleared when adctl is written. bit 6 ? unimplemented always reads 0 scan ? continuous scan control 0 = do four conversions and stop 1 = convert four channels in selected group continuously mult ? multiple channel/single channel control 0 = convert single channel selected 1 = convert four channels in selected group $103c highest priority i bit interrupt and miscellaneous register (hprio) read: rboot smod mda irv(ne) psel3 psel2 psel1 psel0 write: reset: 0 0 0 0 0 1 1 0 $103d ram and i/o mapping register (init) read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset: 0 0 0 0 0 0 0 1 $103e reserved r r r r r r r r $103f system configuration register (config) read: nosec nocop romon eeon write: reset: 0 0 0 0 u u 1 u $103f system configuration register (config) (3) read: ee3 ee2 ee1 ee0 nosec nocop eeon write: reset: 1 1 1 1 u u 1 1 1. can be written only once in first 64 cycles out of re set in normal modes or at any time during special modes. 2. mc68hc711e9 only 3. mc68hc811e2 only addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected i = indeterminate after reset figure 6. register a nd control bit assignments (sheet 6 of 6) address: $1030 bit 7654321bit 0 read: ccf scan mult cd cc cb ca write: reset: 0 0 indeterminate after reset = unimplemented
m68hc11erg/ad 28 m68hc11e series programming reference guide motorola cd:ca ? channel selects d:a refer to the following table. a/d results (adr1?adr4) channel select control bits channel signal result in adrx if mult = 1 result in adrx if mult = 0 cd:cc:cb:ca 0000 an0 adr1 adr[4:1] 0001 an1 adr2 adr[4:1] 0010 an2 adr3 adr[4:1] 0011 an3 adr4 adr[4:1] 0100 an4 adr1 adr[4:1] 0101 an5 adr2 adr[4:1] 0110 an6 adr3 adr[4:1] 0111 an7 adr4 adr[4:1] 10xx reserved ? ? 1100 v rh (1) 1. used for factory testing adr1 adr[4:1] 1101 v rl (1) adr2 adr[4:1] 1110 (v rh )/2 (1) adr3 adr[4:1] 1111 reserved (1) adr4 adr[4:1] adr1 ? address: $1031 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset: indeterminate after reset adr2 ? address: $1032 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset: indeterminate after reset adr3 ? address: $1033 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset: indeterminate after reset adr4 ? address: $1034 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset: indeterminate after reset = unimplemented
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 29 analog input to 8-bit result translation table baud rate control register (baud) tclr ? clear baud rate counter (test) scp[2:0] ? sci baud rate prescaler select scp2 applies to the mc68hc(7)11e20 only. when scp2 = 1, scp[1:0] must equal 0. any other values for scp[1:0] are not decoded in the prescaler and the results are unpredictable. rckb ? sci baud rate clock check (test) bit 7654321bit 0 % (1) 1. % of v rh ?v rl 50% 25% 12.5% 6.25% 3.12% 1.56% 0.78% 0.39% volts (2) 2. voltages for v rl = 0; v rh = 5.0 v 2.500 1.250 0.625 0.3125 0.1562 0.0781 0.0391 0.0195 volts (3) 3. voltages for v rl = 0; v rh = 3.3 v 1.65 8.25 0.4125 0.2063 0.1031 0.0516 0.0258 0.0129 address: $102b bit 7654321bit 0 read: tclr scp2 scp1 scp0 rckb scr2 scr1 scr0 write: reset:00000uuu u = unaffected scp divide internal clock by crystal frequency (mhz) 2 (1) 1. shaded areas apply to mc68hc(7)11e20 only. 1 0 4.0 4.9152 8.0 8.3886 12.0 0 0 0 1 62500 76800 125000 131072 187500 0 0 1 3 20833 25600 41667 43691 62500 0 1 0 4 15625 19200 31250 32768 46875 0 1 1 13 4800 5907 9600 10082 14423 1 0 0 39 1602 1969 3205 3361 4808
m68hc11erg/ad 30 m68hc11e series programming reference guide motorola scr[2:0] ? sci baud rate selects selects receiver and transmitter bit rate based on output from baud rate prescaler stage. refer to sci baud rate generator block diagram. block protect register (bprot) bits [7:5] ? unimplemented always read 0 ptcon ? protect config register 0 = config register can be pr ogrammed or erased normally. 1 = config register cannot be programmed or erased. bprt[3:0] ? block protect for eeprom block protect register bits can be written to 0 (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special modes. block protect register bits can be written to 1 (protection enabled) at any time. 0 = protection disabled for associated block 1 = protection enabled for associated block scr divide prescaler by highest baud rate (prescaler output from previous table 2 1 0 131072 76800 32768 19200 4800 0 0 0 1 131072 76800 32768 19200 4800 0 0 1 2 65536 38400 16384 9600 2400 0 1 0 4 32768 19200 8192 4800 1200 0 1 1 8 16384 9600 4096 2400 600 1 0 0 16 8192 480 2048 1200 300 1 0 1 32 4096 2400 1024 600 150 1 1 0 64 2048 1200 512 300 75 1 1 1 128 1024 600 256 150 37.5 address: $1035 bit 7654321bit 0 read: ptcon bprt3 bprt2 bprt1 bprt0 write: reset:00011111 = unimplemented bit name block protected block size bprt0 $b600?$b61f 32 bytes bprt1 $b620?$b65f 64 bytes bprt2 $b660?$b6df 128 bytes bprt3 $b6e0?$b7ff 288 bytes mc68hc811e2 only bprt0 $x800?$x9ff (1) 1. x is determined by the value of ee [3:0] in config (mc68hc811e2 only). refer to the mc68hc811e2 config register. 512 bytes bprt1 $xa00?$xbff (1) 512 bytes bprt2 $xc00?$xdff (1) 512 bytes bprt3 $xe00?$xfff (1) 512 bytes
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 31 timer compare force register (cforc) foc[1:5] ? force output comparison write 1s to force compare(s). 0 = not affected 1 = output x action occurs bits [2:0] ? unimplemented always read 0 configuration register (config) security disable, cop, ro m mapping, and eeprom enables the following register description applies to the mc68hc11e2 only. address: $100b bit 7654321bit 0 read: foc1 foc2 foc3 foc4 foc5 write: reset:00000000 = unimplemented address: $103f bit 7654321bit 0 read: nosec nocop romon eeon write: resets: single chip: bootstrap: expanded: test: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u 1 1 u u(l) u u(l) 1 u u u u u u u = unimplemented u indicates a previously programmed bit. u(l) indicates that the bit resets to the logic level held in the latch prior to reset , but the function of cop is controlled by the disr bit in test1 register. address: $103f bit 7654321bit 0 read: ee3 ee2 ee1 ee0 nosec nocop eeon write: resets: single chip: bootstrap: expanded: test: 1 1 u u 1 1 u u 1 1 u u 1 1 u u u u 1 1 u u(l) u u(l) 1 1 1 1 1 1 u 0 = unimplemented u indicates a previously programmed bit. u(l) indicates that the bit resets to the logic level held in the latch prior to reset , but the function of cop is controlled by the disr bit in test1 register.
m68hc11erg/ad 32 m68hc11e series programming reference guide motorola ee[3:0] ? eeprom map position (mc68hc811e2 only) ee[3:0] determine the upper four bi ts of eeprom address, positioning eeprom at the selected 4-kbyte boundar y. in single-chip and boot modes, these bits are set to 1s during reset and eeprom is mapped to top of memory. not implemented in other e-series devices; always read 0. refer to the following table. nosec ? security disable nosec is invalid unless the security ma sk option is specified before the mcu is manufactured. if the security ma sk option is omitted nosec always reads 1. the enhanced security featur e is available in the mc68s711e9 mcu. the enhancement to the standard security feature protects the eprom as well as ram and eeprom. 0 = ram/eeprom security mode enabled 1 = ram/eeprom security mode disabled nocop ? cop system disable resets to programmed value. 0 = cop enabled (forces reset on timeout) 1 = cop disabled (does not force reset on timeout) romon ? rom/eprom enable in single-chip mode, romon is forced to 1 out of reset. romon does not apply to the mc68hc811e2. for devices with disabled rom arrays (the mc68hc11e0, mc68hc11e1, mc68l11e0, or mc68l11e1) romon must never be set to 1. 0 = rom/eprom removed from the memory map 1 = rom/eprom present in the memory map eeon ? eeprom enable 0 = eeprom removed from the memory map 1 = eeprom present in the memory map ee3 ee1 ee2 ee0 eeprom location 0000 $08 00?$0fff 0001 $18 00?$1fff 0010 $28 00?$2fff 0011 $38 00?$3fff 0100 $48 00?$4fff 0101 $58 00?$5fff 0110 $68 00?$6fff 0111 $78 00?$7fff 1000 $88 00?$8fff 1001 $98 00?$9fff 1010 $a8 00?$afff 1011 $b8 00?$bfff 1100 $c8 00?$cfff 1101 $d8 00?$dfff 1110 $e8 00?$efff 1111 $f8 00?$ffff
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 33 arm/reset cop timer circuitry register (coprst) write $55 to coprst to arm cop watchdog clearing mechanism. write $aa to coprst to reset cop watchdog. data direction register for port c (ddrc) ddc[7:0] ? data direction for port c in handshake output mode, ddrc bits selected the three-stated output option (ddcx = 1). 0 = input 1 = output data direction register for port d (ddrd) bits [7:6] ? unimplemented always read 0 ddd[5:0] ? data direction for port d 0 = input 1 = output eprom programming control register (eprog) address: $103a bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 address: $1007 bit 7654321bit 0 read: ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 write: reset:00000000 address: $1009 bit 7654321bit 0 read: ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 write: reset:00000000 unimplemented address: $1036 bit 7654321bit 0 read: mbe elat excol exrow t1 t0 pgm write: reset:00000000 = unimplemented
m68hc11erg/ad 34 m68hc11e series programming reference guide motorola note: eprog is present only on the mc68hc711e20. mbe ? multiple-byte programming enable when multiple-byte programming is e nabled, address bit 5 is considered a don?t care so that bytes with address bit 5 = 0 and address bit 5 = 1 both get programmed. mbe can be read in any mode and always reads 0 in normal modes. mbe can be written only in special modes. 0 = eprom array configured for normal programming 1 = program two bytes with the same data bit 6 ? unimplemented always reads 0 elat ? eprom/otprom latch control when elat = 1, writes to eprom cause address and data to be latched and the eprom/otprom cannot be re ad. elat can be read any time. elat can be written any time except when pgm = 1; then the write to elat is disabled. 0 = eprom/otprom address and data bus configured for normal reads 1 = eprom/otprom address and data bus configured for programming excol ? select extra columns 0 = user array selected 1 = user array is disabled and extra columns are accessed at bits [7:0]. addresses use bits [13:5] and bits [4:0] are don?t care. excol can be read and written only in special modes and always returns 0 in normal modes. exrow ? select extra rows 0 = user array selected 1 = user array is disabled and two ex tra rows are available. addresses use bits [7:0] and bits [13:8] are don?t care. exrow can be read and written only in special modes and always returns 0 in normal modes. t[1:0] ? eprom test mode select these bits allow selection of either gate stress or drain stress test modes. they can be read and written only in special modes and always read 0 in normal modes. pgm ? eprom programming voltage enable pgm can be read any time and can be written only when elat = 1. 0 = programming voltage to eprom array disconnected 1 = programming voltage to eprom array connected t1 t0 function selected 0 0 normal mode 0 1 reserved 1 0 gate stress 1 1 drain stress
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 35 highest priority i bit interrupt and miscellaneous (hprio) rboot ? read bootstrap rom valid only when smod is set to 1 (bootstrap or special test mode). can only be written in special modes. 0 = bootloader rom disabled and not in map 1 = bootloader rom enabled and in map at $be00?$bfff smod and mda ? special mode select and mode select a the initial value of smod is in the inverse of the logic level present on the modb pin at the rising edge of reset. the initial value of mda equals the logic level present on the moda pin at the rising edge of reset. these two bits can be read at any time. they can be written anytime in special modes. mda can only be written once in normal modes. smod cannot be set once it has been cleared. refer to the following table. irvne ? internal read visibility /not e (irv in mc68hc811e2) irvne can be written once in any mode. in expanded modes, irvne determines whether irv is on or off. in special test mode, irvne is reset to 1. for the mc68hc811e2, this bit co ntrols only internal read visibility function and has no meaning or effect in single-chip modes. 0 = no internal read visi bility on external bus 1 = data from internal reads is driven out the external data bus in single-chip modes this bit determine s whether the e clock drives out from the chip. 0 = e is driven out from the chip. 1 = e pin is driven low. refer to the following table. address: $103c bit 7654321bit 0 read: rboot (1) smod (1) mda (1) irvne psel3 psel2 psel1 psel0 write: reset: single chip: expanded: bootstrap: special test: 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1. the values of the rboot, smod, and mda re set bits depend on the mode selected at the reset pin rising edge. inputs mode latched at reset modb moda smod mda 10single chip 0 0 1 1 expanded 0 1 0 0 bootstrap 1 0 01special test1 1 mode irvne out of reset e clock out of reset irv out of reset irvne affects only irvne can be written single chip 0 on off e once expanded 0 on off irv once bootstrap 0 on off e once special test 1 on on irv once
m68hc11erg/ad 36 m68hc11e series programming reference guide motorola note: when irv function is used, care must be taken to ensure that bus conflicts do not occur. data can be driven onto the bus even though the r/w line indicates a high-impedance state on data bus pins. psel[3:0] ? priority select can be written only while bit i in the ccr is set (interrupts disabled). these bits select one interrupt source to be elevated above all other i bit related sources. refer to the following table. ram and register mapping (init) ram[3:0] ? internal ram map position determine the upper four bits of ram address. at reset, ram is mapped to $0000. psel3 psel2 psel1 psel0 interrupt source promoted 0000timer overflow 0 0 0 1 pulse accumulator overflow 0 0 1 0 pulse accumulator input edge 0 0 1 1 spi serial transfer complete 0 1 0 0 sci serial system 0 1 0 1 reserved (default to irq ) 0110irq (external pin or parallel i/o) 0 1 1 1 real-time interrupt 1 0 0 0 timer input capture 1 1 0 0 1 timer input capture 2 1 0 1 0 timer input capture 3 1 0 1 1 timer output compare 1 1 1 0 0 timer output compare 2 1 1 0 1 timer output compare 3 1 1 1 0 timer output compare 4 1 1 1 1 timer input capture 4/output compare 5 address: $103d bit 7654321bit 0 read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset:00000001 ram[3:0] address ram[3:0] address 0000 $0000?$0xff 1000 $8000?$8xff 0001 $1000?$1xff 1001 $9000?$9xff 0010 $2000?$2xff 1010 $a000?$axff 0011 $3000?$3xff 1011 $b000?$bxff 0100 $4000?$4xff 1100 $c000?$cxff 0101 $5000?$5xff 1101 $d000?$dxff 0110 $6000?$6xff 1110 $e000?$exff 0111 $7000?$7xff 1111 $f000?$fxff
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 37 reg[3:0] ? 64-byte register block map position determine upper four bits of register space address. at reset, registers are mapped to $1000. note: can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes. output compare 1 data register (oc1d) if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits [2:0]? unimplemented always reads 0 output compare 1 mask register (oc1m) oc1m[7:3] ? output compare masks 0 = oc1 disabled 1 = oc1 enabled to control the corresponding pin of port a bits [2:0]? unimplemented always reads 0 reg[3:0] address reg[3:0] address 0000 $0000?$003f 1000 $8000?$803f 0001 $1000?$103f 1001 $9000?$903f 0010 $2000?$203f 1010 $a000?$a03f 0011 $3000?$303f 1011 $b000?$b03f 0100 $4000?$403f 1100 $c000?$c03f 0101 $5000?$503f 1101 $d000?$d03f 0110 $6000?$603f 1110 $e000?$e03f 0111 $7000?$703f 1111 $f000?$f03f address: $100d bit 7654321bit 0 read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 write: reset:00000000 unimplemented address: $100c bit 7654321bit 0 read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 write: reset:00000000 unimplemented
m68hc11erg/ad 38 m68hc11e series programming reference guide motorola system configuration options (option) adpu ? analog-to-digital (a/d) converter power-up 0 = a/d powered down 1 = a/d powered up csel ? clock select 0 = a/d and eeprom charge pumps use system e clock 1 = a/d and eeprom charge pumps use internal rc oscillator irqe ? irq select edge-sensitive only 0 = low level recognition 1 = falling edge recognition dly ? enable oscillator startup delay on exit from stop mode 0 = no stabilization delay on exit from stop mode 1 = stabilization delay enabled on exit from stop mode cme ? clock monitor enable 0 = clock monitor disabled; slow clocks can be used 1 = slow or stopped clocks cause clock failure reset bit 2 ? not implemented always reads 0 cr[1:0] ? cop timer rate select refer to the following table. pulse accumulator counter (pacnt) address: $1039 bit 7654321bit 0 read: adpu csel irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset:00010000 1. can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes. = unimplemented cr[1:0] divide e/2 15 by xtal = 4.0 mhz timeout ? 0 ms, + 32.8 ms xtal = 8.0 mhz timeout ? 0 ms, + 16.4 ms xtal = 12.0 mhz timeout ? 0 ms, + 10.9 ms xtal = 16.0 mhz timeout ? 0 ms, + 8.2 ms 0 0 1 32.768 ms 16.384 ms 10.923 ms 8.19 ms 0 1 4 131.072 ms 65.536 ms 43.691 ms 32.8 ms 1 0 16 524.28 ms 262.14 ms 174.76 ms 131 ms 1 1 64 2.098 s 1.049 s 699.05 ms 524 ms e = 1.0 mhz 2.0 mhz 3.0 mhz 4.0 mhz address: $1027 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: unaffected by reset
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 39 pulse accumulator control (pactl) ddra7 ? data direction for port a bit 7 0 = input only 1 = output paen ? pulse accumula tor system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ? pulse accumulator mode 0 = event counter 1 = gated time accumulation pedge ? pulse accumulator edge control refer to the following table. ddra3 ? data direction for port a bit 3 overridden if an output compare function is configured to control the pa3 pin. 0 = input 1 = output i4/o5 ? input capture 4/output compare 5 configure ti4/o5 for input capture or output compare 0 = oc5 enabled 1 = ic4 enabled rtr[1:0] ? real-time interrupt (rti) rate refer to the following table. address: $1026 bit 7654321bit 0 read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 pamod pedge acti on on clock 0 0 pai falling edge increments the counter. 0 1 pai rising edge increments the counter. 1 0 a zero on pai inhibits counting. 1 1 a one on pai inhibits counting. rtr1 rtr0 e = 3 mhz e = 2 mhz e = 1 mhz e = x mhz 0 0 2.731 ms 4.096 ms 8.192 ms (e/2 13 ) 0 1 5.461 ms 8.192 ms 16.384 ms (e/2 14 ) 1 0 10.923 ms 16.384 ms 32.768 ms (e/2 15 ) 1 1 21.845 ms 32.768 ms 65.536 ms (e/2 16 )
m68hc11erg/ad 40 m68hc11e series programming reference guide motorola parallel i/o control (pioc) staf ? strobe a interrupt status flag staf is set when the selected edge occurs on strobe a. this bit can be cleared by a read of pioc with staf set followed by a read of portcl (simple strobed or full input handshake mode) or a write to portcl (output handshake mode). 0 = no active edge detected 1 = selected active edge detected stai ? strobe a interrupt enable mask 0 = staf does not request interrupt 1 = staf requests interrupt cwom ? port c wired-or mode (affects all eight port c pins) 0 = port c outputs are normal cmos outputs. 1 = port c outputs are open-drain outputs. hnds ? handshake mode bit 0 = simple strobe mode 1 = full input or output handshake mode oin ? output or input handshake select hnds must be set to 1 for this bit to have meaning. 0 = input handshake 1 = output handshake pls ? pulsed/interlocked handshake operation hnds must be set to 1 for this bit to have meaning. when interlocked handshake is selected, strobe b is active until the selected edge of strobe a is detected. 0 = interlocked handshake 1 = pulsed handshake (strobe b pulse s high for two e-clock cycles.) ega ? active edge for strobe a 0 = stra falling edge selected 1 = stra rising edge selected invb ? invert strobe b 0 = active level is logic 0. 1 = active level is logic 1. address: $1002 bit 7654321bit 0 read: staf stai cwom hnds oin pls ega invb write: reset:00000u11 u = unaffected
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 41 port a data register (porta) note: i/o pins configured as high-impedance inputs have port data that is indeterminate. the contents of the corresponding latches are dependent upon the electrical state of the pins during reset. this is indicated by an ?i? in the port description. port b data register (portb) staf clearing sequence hnds oin pls ega port b port c simple strobed mode read pioc with staf = 1 then read portcl 0x x inputs latched into portcl on any active edge on stra strb pulses on writes to portb full-input hand- shake mode read pioc with staf = 1 then read portcl 10 0 = strb active level 1 = strb active pulse inputs latched into portcl on any active edge on stra normal output port, unaffected in handshake modes full- output hand- shake mode read pioc with staf = 1 then write portcl 11 0 = strb active level 1 = strb active pulse driven as outputs if stra at active level; follows ddrc if stra not at active level normal output port, unaffected in handshake modes 1 0 0 1 0 1 port c driven stra active edge follow ddrc follow ddrc address: $1000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: alt. pin function: and/or i pai oc1 0 oc2 oc1 0 oc3 oc1 0 oc4 oc1 i oc5/ic4 oc1 i ic1 ? i ic2 ? i ic3 ? address: $1004 bit 7654321bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb2 pb0 write: reset: single chip or boot: expanded or test: 0 pb7 addr15 0 pb6 addr14 0 pb5 addr13 0 pb4 addr12 0 pb3 addr11 0 pb2 addr10 0 pb1 addr9 0 pb0 addr8
m68hc11erg/ad 42 m68hc11e series programming reference guide motorola port c data register (portc) port c latched data register (portcl) port d data register (portd) port e data register (porte) eeprom programming control register (pprog) odd ? program odd rows in half of eeprom (test) even ? program even rows in half of eeprom (test) bit address: $1003 bit 7654321bit 0 read: pc7pc6pc5pc4pc3pc2pc2pc0 write: reset: single chip or boot: expanded or test: 0 pc7 data7 0 pc6 data6 0 pc5 data5 0 pc4 data4 0 pc3 data3 0 pc2 data2 0 pc1 data1 0 pc0 data0 address: $1005 bit 7654321bit 0 read: pcl7 pcl6 pcl5 pcl4 pcl3 pcl2 pcl1 pcl0 write: reset: indeterminate after reset address: $1008 bit 7654321bit 0 read: pd5pd4pd3pd2pd1pd0 write: reset: alt. pin function 0 ? 0 ? i ss i sck i sdo/mosi i sdi/miso i txd i rxd = unimplemented address: $100a bit 7654321bit 0 read: pe7 pe6 pd5 pe4 pe3 pe2 pe1 pe0 write: reset: alt. pin function i an7 i an6 i an5 i an4 i an3 i an2 i an1 i an0 address: $103b bit 7654321bit 0 read: odd even elat (1) byte row erase eelat epgm write: reset:00000000 1. mc68hc711e9 and mc68s711e9 only
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 43 elat ? eprom/otprom latch control implemented on mc68hc711e9 only 0 = eprom/otprom address and data bus configured for normal reads and cannot be programmed 1 = eprom/otprom address and data bus configured for programming and cannot be read byte ? byte/other eeprom erase mode 0 = row or bulk erase mode used 1 = erase only one byte of eeprom row ? row/all eeprom erase mode only valid when byte = 0 0 = erase all of eeprom 1 = erase only one 16-byte row of eeprom erase ? erase/normal control for eeprom 0 = normal read or program mode 1 = erase mode eelat ? eeprom latch control 0 = eeprom address and data bus configured for normal reads 1 = eeprom address and data bu s configured for programming or erasing epgm ?eprom/eeprom programming voltage enable 0 = programming voltage to arra y disconnected (eeprom only on mc68hc(7)11e20) 1 = programming voltage to array connected (eeprom only on mc68hc(7)11e20) serial communication interface control register 1 (sccr1) r8 ? receive data bit 8 0 = sci receiver configured for 8-bit data characters. 1 = if m bit is set, r8 stores the ninth data bit in the receive data character. byte row action 0 0 bulk erase (all bytes) 0 1 row erase (16 bytes) 1 0 byte erase 1 1 byte erase address: $102c bit 7654321bit 0 read: r8 t8 m write: reset:i i 000000 = unimplemented
m68hc11erg/ad 44 m68hc11e series programming reference guide motorola t8 ? transmit data bit 8 0 = sci transmitter configured for 8-bit data characters. 1 = if m bit is set, r8 stores the ninth data bit in the transmit data character. bit 5 ? unimplemented always reads 0 m ? mode bit (select character format) 0 = start bit, 8 data bits, 1 stop bit 1 = start bit, 9 data bits, 1 stop bit wake ? wakeup by address mark/idle 0 = wakeup by idle line recognition 1 = wakeup by address mark (mos t significant data bit set) bits [2:0] ? unimplemented always read 0 serial communications interface control register 2 (sccr2) tie ? transmit interrupt enable 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ? transmit complete interrupt enable 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ? receiver interrupt enable 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set ilie ? idle-line interrupt enable 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ? transmitter enable 0 = transmitter disabled 1 = transmitter enabled re ? receiver enable 0 = receiver disabled 1 = receiver enabled rwu ? receiver wakeup control 0 = normal sci receiver 1 = wakeup enabled and receiver interrupts inhibited sbk ? send break 0 = break generator off 1 = break codes generated as long as sbk = 1 address: $102d bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 45 serial communications interface data register (scdr) r[7:0]/t[7:0] ? receiver/tra nsmitter data bits [7:0] receive and transmit are double buffered. reads access the receive data buffer, and writes access the transmit data buffer. when the m bit in sccr1 is set, r8 and t8 in sccr1 store the ninth bit in receive and transmit data characters. serial communications interface status register (scsr) tdre ? transmit data register empty flag this flag is set when scdr is empty. clear the tdre flag by reading scsr with tdre set and then writing to scdr. 0 = scdr busy 1 = scdr empty tc ? transmit complete flag this flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). clear the tc flag by reading scsr with tc set and then writing to scdr. 0 = transmitter busy 1 = transmitter idle rdrf ? receive data register full flag this flag is set if a received characte r is ready to be read from scdr. clear the rdrf flag by reading scsr wi th rdrf set and then reading scdr. 0 = scdr empty 1 = scdr full idle ? idle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and beco mes idle again. the idle flag is inhibited when rwu = 1. clear idle by reading scsr with idle set and then reading scdr. 0 = rxd line active 1 = rxd line idle address: $102f bit 7654321bit 0 read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset:iiiiiiii address: $102e bit 7654321bit 0 read: tdre tc rdrf idle or nf fe write: reset:11000000 = unimplemented
m68hc11erg/ad 46 m68hc11e series programming reference guide motorola or ? overrun error flag or is set if a new character is re ceived before a previously received character is read from scdr. clear the or flag by reading scsr with or set and then reading scdr. 0 = no overrun 1 = overrun detected nf ? noise error flag nf is set if majority sample logi c detects anything other than a unanimous decision. clear nf by reading scsr with nf set and then reading scdr. 0 = unanimous decision 1 = noise detected fe ? framing error flag fe is set when a 0 is detected where a stop bit was expected. clear the fe flag by reading scsr with fe set and then reading scdr. 0 = stop bit detected 1 = zero detected bit 0 ? unimplemented always reads 0 serial peripheral interface control register (spcr) spie ? serial peripheral interrupt enable 0 = spi interrupts disabled 1 = spi interrupts enabled spe ? serial peripheral system enable 0 = spi off 1 = spi on dwom ? port d wired-or mode option for port d pins pd[5:0] 0 = normal cmos outputs 1 = open-drain outputs mstr ? master mode select 0 = slave mode 1 = master mode cpol, cpha ? clock polarity, clock phase refer to figure 7 spr[1:0] ? spi clock rate select see the following table. address: $1028 bit 7654321bit 0 read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset:000001uu
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 47 figure 7. serial peripheral interface transfer format serial peripheral interface data register (spdr) spi is double buffered in, single buffered out. spr1 spr0 divide e clock by frequency at e = 1 mhz (baud) frequency at e = 2 mhz (baud) frequency at e = 3 mhz (baud) frequency at e = 4 mhz (baud) 0 0 2 500 khz 1.0 mhz 1.5 mhz 2 mhz 0 1 4 250 khz 500 khz 750 khz 1 mhz 1 0 16 62.5 khz 125 khz 187.5 khz 250 khz 1 1 32 31.3 khz 62.5 khz 93.8 khz 125 khz 2345678 1 sck (cpol = 1) sck (cpol = 0) sck cycle # ss (to slave) 654321 lsb msb msb654321lsb 1 2 3 5 4 slave cpha = 1 transfer in progress master transfer in progress slave cpha = 0 transfer in progress 1. ss asserted 2. master writes to spdr 3. first sck edge 4. spif set 5. ss negated sample input data out (cpha = 0) sample input data out (cpha = 1) address: $102a bit 7654321bit 0 read: bit 7 6 5 4 321bit 0 write:
m68hc11erg/ad 48 m68hc11e series programming reference guide motorola serial peripheral interface status register (spsr) spif ? spi transfer complete flag this flag is set when an spi transfer is complete (after eight sck cycles in a data transfer). clear this flag by reading spsr (with spif = 1), then access spdr. 0 = no spi transfer complete or spi transfer still in progress 1 = spi transfer complete wcol ? write collision this flag is set if the mcu tries to write data into spdr while an spi data transfer is in progress. clear this flag by reading spsr (with wcol = 1), then access spdr. 0 = no write collision error 1 = spdr written while spi transfer in progress bit 5 ? unimplemented always reads 0 modf ? mode fault (mode fault terminates spi operation) modf is set when ss is pulled low while mstr = 1. clear this flag by reading spcr with modf set, then write to spcr. 0 = no mode fault error 1 = ss pulled low in master mode bits [3:0] ? unimplemented always reads 0 timer count register (tcnt) in normal modes, tcnt is a read-only register. address: $1029 bit 7654321bit 0 read: spif wcol modf write: reset:000001uu = unimplemented address: $100e ? high bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 address: $100f ? low bit 7654321bit 0 read: bit 7 6 5 4 321bit 0 write: reset:00000000 = unimplemeted
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 49 timer control register 1 (tctl1) om[2:5] ? output mode ol[2:5] ? output level timer control register 2 (tctl2) factory test register (test1) tilop ? test illegal opcode (test modes only) bit 6 ? unimplemented always reads 0 occr ? output condition code register to timer port (test modes only) cbyp ? timer divider chain bypass (test modes only) disr ? disable reset from cop and clock monitor (special modes only (smod = 1)) address: $1020 bit 7654321bit 0 read: om2 ol2 om3 ol3 om4 ol4 om5 ol5 write: reset:00000000 omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to 0 1 1 set ocx output line to 1 address: $1021 bit 7654321bit 0 read: edg4b edg4a edg1b edg1a edg2b edg1b edg3b edg3a write: reset:00000000 edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge address: $103e bit 7654321bit 0 read: tilop occr cbyp disr fcm fcop tcon write: reset:0000?000 = unimplemented
m68hc11erg/ad 50 m68hc11e series programming reference guide motorola fcm ? force clock monitor failure (test modes only) fcop ? force cop watchdog failure (test modes only) tcon ? test configuration (test modes only) timer interrupt flag 1 register (tflg1) clear flags by writing a 1 to the corresponding bit position(s). oc1f?oc4f ? output compare x flag set each time the counter matches output compare x value. i4/o5f ? input capture 4/output compare 5 flag set by ic4 or oc5, depending on which function was enabled by i4/o5 of pactl. ic1f?ic3f ? input capture x flag set each time a selected active edge is detected on the icx input line. timer interrupt flag 2 register (tflg2) clear flags by writing a 1 to the corresponding bit position(s). tof ? timer overflow flag set when tcnt changes from $ffff to $0000 rtif ? real-time (periodic) interrupt flag the rtif status bit is automatically set to 1 at the end of every rti period. to clear rtif, write a byte to tflg2 with bit 6 set. paovf ? pulse accumulator overflow flag set when pacnt changes from $ff to $00 paif ? pulse accumulator input edge flag set each time a selected active edge is detected on the pai input line. bits [3:0] ? unimplemented always reads 0 address: $1023 bit 7654321bit 0 read: oc1f oc2f oc3f oc4f ir/o5f ic1f 1c2f ic3f write: reset:00000000 address: $1025 bit 7654321bit 0 read: tof rtif paov f pa if write: reset:00000000 = unimplemented
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 51 timer input capture 4/output compare 5 register (ti4/o5) timer input capture registers (tic1?tic3) address: $101e ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $101f ? low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset:11111111 tic1 ? address: $1010 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $1011 ? low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset: unaffected by reset tic2 ? address: $1012 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $1013 ? low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset: unaffected by reset tic3 ? address: $1014 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $1015 ? low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset: unaffected by reset
m68hc11erg/ad 52 m68hc11e series programming reference guide motorola timer interrupt mask register 1 (tmsk1) oc1i?oc4i ? output compare x interrupt enable if the ocxi enable bit is set when the ocxf flag bit is set, a hardware interrupt sequence is requested. i4/o5i ? input capture 4/output compare 5 interrupt enable when i4/o5 in pactl is 1, i4/o5i is the input capture 4 interrupt enable bit. when i4/o5 in pactl is 0, i4/o5i is the output compare 5 interrupt enable bit. ic1i?ic3i ? input capture x interrupt enable if the icxi enable bit is set when the icxf flag bit is set, a hardware interrupt sequence is requested. timer interrupt mask register 2 (tmsk2) toi ? timer overflow interrupt enable 0 = tof interrupts disabled 1 = interrupt requested when tof is set to 1 rtii ? real-time interrupt enable 0 = rtif interrupts disabled 1 = interrupt requested when rtif is set to 1 paovi ? pulse accumulator input edge interrupt enable 0 = paovf interrupts disabled 1 = interrupt requested when paovf is set to 1 paii ? pulse accumulator input edge interrupt enable 0 = paif interrupts disabled 1 = interrupt requested when paif is set to 1 bits [3:2] ? unimplemented always reads 0 pr[1:0] ? timer prescaler select in normal modes, pr1 and pr0 can only be written once, and the write must occur within 64 cycles after reset. address: $1022 bit 7654321bit 0 read: oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i write: reset:00000000 address: $1024 bit 7654321bit 0 read: toi rtii paovi paii pr1 pr0 write: reset:00000000 = unimplemented pr1 pr0 prescaler 00 1 01 4 10 8 11 16
m68hc11erg/ad m68hc11e series registers motorola m68hc11e series programming reference guide 53 timer output compare registers (toc1?toc4) toc1 ? address: $1016 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $1017 ? low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset:11111111 toc2 ? address: $1018 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $1019 ? low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset:11111111 toc3 ? address: $101a ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $101b ? low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset:11111111 toc4 ? address: $101c ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 write: reset:11111111
m68hc11erg/ad 54 m68hc11e series programming reference guide motorola m68hc11 e series pin assignments figure 8. pin assignments for 52-pin plcc and clcc figure 9. pin assignments for 52-pin tqfp pe4/an4 pe0/an0 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 pa0/ic3 extal strb/r/w e stra/as moda/lir modb/v stby v ss v rh v rl pe7/an7 pe3/an3 xtal pc0/addr0/data0 pc1/addr1/data1 pc2/addr2/data2 pc3/addr3/data3 pc4/addr4/data4 pc5/addr5/data5 pc6/addr6/data6 pc7/addr7/data7 reset * xirq /v ppe pd1/txd pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/pai/oc1 pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 m68hc11 e series 8 9 10 11 12 13 14 15 16 17 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 7 6 5 4 3 1 2 52 51 50 49 irq 18 pd0/rxd 19 pa2/ic1 32 pa1/ic2 33 pe6/an6 48 pe2/an2 47 pe1/an1 45 pe5/an5 46 20 * v ppe applies only to devices with eprom/otprom . pa0/ic3 pb7/addr15 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe0/an0 pe4/an4 pe1/an1 pe5/an5 pa1/ic2 pa2/ic1 pa3/oc5/ic4/oc1 pa4/oc4/oc1 pa5/oc3/oc1 pa6/oc2/oc1 pa7/pai/oc1 pd5/ss v dd pd4/sck pd3/mosi pd2/miso m68hc11 e series 52 1 2 3 4 5 6 7 8 9 51 50 49 48 47 46 45 44 42 10 11 43 12 13 41 40 pe2/an2 pe6/an6 pe3/an3 pe7/an7 v rl v rh v ss modb/v stby moda/lir stra/as e strb/r/w extal 14 15 16 17 18 19 20 21 22 24 23 25 26 pd0/rxd irq xirq /v ppe * reset pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc3/addr3/data3 pc4/addr4/data4 pc2/addr2/data2 pc1/addr1/data1 pc0/addr0/data0 xtal 39 38 37 36 35 34 33 32 31 29 30 28 * v ppe applies only to devices with eprom/otprom. 27 pd1/txd
m68hc11erg/ad m68hc11 e series pin assignments motorola m68hc11e series programming reference guide 55 figure 10. pin assignments for 64-pin qfp pa0/ic3 nc nc nc pb7/addr15 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe0/an0 pe4/an4 pe1/an1 pe5/an5 pe2/an2 pe6/an6 pe3/an3 pe7/an7 v rl v rh v ss v ss modb/v stby moda/lir nc stra/as e strb/r/w nc nc pd0/rxd irq xirq /v ppe * nc reset pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc3/addr3/data3 pc4/addr4/data4 pc2/addr2/data2 pc1/addr1/data1 nc pc0/addr0/data0 xtal pa1/ic2 pa2/ic1 pa3/oc5/ic4/oc1 nc nc pa4/oc4/oc1 pa5/oc3/oc1 pa6/oc2/oc1 pa7/pai/oc1 pd5/ss v dd pd4/sck pd3/mosi pd2/miso pd1/txd v ss m68hc11 e series 64 1 2 3 4 5 6 7 8 9 17 18 19 20 21 22 23 24 25 27 63 62 61 60 59 58 57 56 54 10 11 48 47 46 45 44 43 42 41 40 38 39 55 26 12 13 14 15 16 37 36 35 34 33 28 29 30 31 32 53 52 51 50 49 * v ppe applies only to devices with eprom/otprom. extal
m68hc11erg/ad 56 m68hc11e series programming reference guide motorola figure 11. pin assignments for 56-pin sdip * v ppe applies only to devices with eprom/otprom. pc0/addr0/data0 pc1/addr1/data1 pc2/addr2/data2 pc3/addr3/data3 pc4/addr4/data4 pc5/addr5/data5 pc6/addr6/data6 pc7/addr7/data7 reset * xirq /v ppe m68hc11 e series 9 10 11 12 13 14 15 16 17 18 irq 19 pd0/rxd 20 21 pd1/txd 22 pd2/miso 23 pd3/mosi 24 pd4/sck 25 pd5/ss 26 v dd 27 v ss 28 xtal 8 extal 7 strb/r/w 6 5 stra/as 4 moda/lir 3 modb/v stby 2 v ss 1 pe0/an0 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 pa0/ic3 pa1/ic2 46 45 44 43 42 41 40 39 38 37 36 pe4/an4 47 pe1/an1 48 pa2/ic1 35 pa3/oc5/ic4/oc1 34 pa4/oc4/oc1 33 pa5/oc3/oc1 32 pa6/oc2/oc1 31 pa7/pai/oc1 30 ev dd 29 pe5/an5 49 pe2/an2 50 pe6/an6 51 pe3/an3 52 pe7/an7 53 v rl 54 v rh 55 ev ss 56 ev ss e
m68hc11erg/ad m68hc11 e series pin assignments motorola m68hc11e series programming reference guide 57 figure 12. pin assignments for 48-pin dip (mc68hc811e2) pb7/addr15 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe0/an0 pe1/an1 mc68hc811e2 9 10 11 12 13 14 15 16 17 18 pe2/an2 19 pe3/an3 20 21 v rh 22 v ss 23 modb/v stby 24 pa0/ic3 8 pa1/ic2 7 pa2/ic1 6 pa3/oc5/ic4/oc1 5 pa4/oc4/oc1 4 pa5/oc3/oc1 3 pa6/oc2/oc1 2 pa7/pai/oc1 1 pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc4/addr4/data4 pc3/addr3/data3 pc2/addr2/data2 pc1/addr1/data1 pc0/addr0/data0 xtal extal strb/r/w 38 37 36 35 34 33 32 31 30 29 28 reset 39 xirq 40 e 27 stra/as 26 moda/lir 25 irq 41 pd0/rxd 42 pd1/txd 43 pd2/miso 44 pd3/mosi 45 pd4/sck 46 pd5/ss 47 v dd 48 v rl
m68hc11erg/ad 58 m68hc11e series programming reference guide motorola hexadecimal to ascii conversion table 2. hexadecimal to ascii conversion hex ascii hex ascii hex ascii hex ascii $00 nul $20 sp space $40 @ $60 ` grave $01 soh $21 ! $41 a $61 a $02 stx $22 ? quote $42 b $62 b $03 etx $23 # $43 c $63 c $04 eot $24 $ $44 d $64 d $05 enq $25 % $45 e $65 e $06 ack $26 & $46 f $66 f $07 bel beep $27 ? apost . $47 g $67 g $08 bs back sp $28 ( $48 h $68 h $09 ht tab $29 ) $49 i $69 i $0a lf linefeed $2a * $4a j $6a j $0b vt $2b + $4b k $6b k $0c ff $2c , comma $4c l $6c l $0d cr return $2d - dash $4d m $6d m $0e so $2e . period $4e n $6e n $0f si $2f / $4f o $6f o $10 dle $30 0 $50 p $70 p $11 dc1 $31 1 $51 q $71 q $12 dc2 $32 2 $52 r $72 r $13 dc3 $33 3 $53 s $73 s $14 dc4 $34 4 $54 t $74 t $15 nak $35 5 $55 u $75 u $16 syn $36 6 $56 v $76 v $17 etb $37 7 $57 w $77 w $18 can $38 8 $58 x $78 x $19 em $39 9 $59 y $79 y $1a sub $3a : $5a z $7a z $1b escape $3b ; $5b [ $7b { $1c fs $3c < $5c \ $7c | $1d gs $3d = $5d ] $7d } $1e rs $3e > $5e ^ $7e ~ $1f us $3f ? $5f _ under $7f del delete
m68hc11erg/ad hexadecimal to decimal conversion motorola m68hc11e series programming reference guide 59 hexadecimal to decimal conversion to convert a hexadecimal number (up to four hexadecimal digits) to decimal, look up the decimal equivalent of each hexadecimal digit in table 3 . the decimal equivalent of the original hexadecimal number is the sum of the weights found in the table for all hexadecimal digits. decimal to hexadecimal conversion to convert a decimal number (up to 65,535 10 ) to hexadecimal, find the largest decimal number in table 3 that is less than or equal to the number you are converting. the correspondi ng hexadecimal digit is the most significant hexadecimal digit of the result. subtract the decimal number found from the original decimal number to get the remaining decimal value . repeat the procedure using the remaining dec imal value for each subsequent hexadecimal digit. table 3. hexadecimal to/from decimal conversion 15 bit 8 7bit0 15 12 11 8 74 30 4th hex digit 3rd hex digit 2nd hex digit 1st hex digit hex decimal hex decimal hex decimal hex decimal 0 0 0 0 0 0 0 0 1 4,096 1 256 1 16 1 1 2 8,192 2 512 2 32 2 2 3 12,288 3 768 3 48 3 3 4 16,384 4 1,024 4 64 4 4 5 20,480 5 1,280 5 80 5 5 6 24,576 6 1,536 6 96 6 6 7 28,672 7 1,792 7 112 7 7 8 32,768 8 2,048 8 128 8 8 9 36,864 9 2,304 9 144 9 9 a 40,960 a 2,560 a 160 a 10 b 45,056 b 2,816 b 176 b 11 c 49,152 c 3,072 c 192 c 12 d 53,248 d 3,328 d 208 d 13 e 57,344 e 3,484 e 224 e 14 f 61,440 f 3,840 f 240 f 15
m68hc11erg/ad how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors m68hc11erg/ad rev. 2 10/2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any produc t or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damage s. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intende d for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2003

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